A composite analog to digital converter (ADC or A-to-D) is a device comprising a plurality of ADCs. Each of the ADC components is configured to convert an analog signal to digital. An analog signal is processed by the ADCs, and the outputs of the ADCs are combined to generate a composite digital output signal. The composite ADC can be used in a wide range of applications such as communications and digital imaging. It can achieve high performance at a relatively low cost since the ADC components are often less expensive devices with lower performance.
FIG. 1A illustrates a composite ADC embodiment. In the example shown, composite ADC 100 is arranged in an interleaving configuration. ADCs 1-N each have a sampling rate of Fs. The analog input signal y is sampled and selectively switched into the ADCs, via a switch 104, at a sampling rate of NFs. The outputs of the ADCs are selected by a switch 106 and interleaved into an output sequence yn, at a rate of NFs. Thus, interleaving allows a high speed composite ADC to be constructed using a number of lower speed ADCs.
FIG. 1B illustrates another composite ADC embodiment. Composite ADC 150 is in a parallel configuration in this example. ADC components 1-N each have a sampling rate of Fs. The input signal y is sent to all the ADCs simultaneously, and the sampled outputs are summed at 152. The combined signal strength is N times the signal strength of one ADC. The resulting noise, however, only increases at ½ the rate of the signal strength increase. Thus, the resulting signal has a higher signal to noise ratio than the individual ADC components.
Although composite ADCs offer performance gains, mismatch in the component ADCs, including mismatch in clock phase, signal path gain, and/or device characteristics often leads to signal distortions. FIGS. 2A-2B are signal diagrams illustrating the effects of the mismatches in example composite ADCs that include two component ADCs. FIG. 2A shows the signal diagrams of an interleaved composite ADC example. The input switched into the ADCs is controlled by a clock that has a duty cycle of approximately 50%. Signals yA and yB are outputs of components ADC1 and ADC2, respectively. The sampling point are shown for purposes of illustration and do not necessarily correspond to the actual sampling rate. Ideally, the sampling phases for the two ADCs are at 50% duty cycle. In practice, however, there is a phase offset of □ between the samples of the two ADCs, as well as an amplitude offset. Thus, there is distortion in the composite signal 200 attributed to aliasing in the resulting composite signal yn. The frequency domain diagram shows desired signal 202 and aliased image 204.
Similarly, in FIG. 2B where the signal diagrams of a parallel composite ADC example are shown, there is an offset in the samples of the two ADCs, causing aliasing effects in the output signal yn. In the frequency domain diagram, images 212 and 214 correspond to the desired signal and the aliased image, respectively. The aliased image is undesirable since it may cause interference with adjacent frequency channels. Furthermore, since the frequency location of the aliased image is not necessarily known a priori and may vary over time, it would be difficult to configure a conventional error correction filter to compensate for the distortion.
It would be useful, therefore, to have a technique for correcting output distortions in composite ADCs. It would also be desirable if the technique is flexible enough to compensate for distorted outputs at unknown, varying frequency locations.